Programmable integrated circuits (ICs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of programmable IC, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). Some FPGAs also include additional logic blocks with special purposes (e.g., DLLs, RAM, and so forth).
The signals between the various logic blocks are interconnected through a programmable interconnect structure that includes a number of configurable interconnect signal lines. Logic blocks are connectable to specific interconnect signal lines using programmable interconnect circuits. One typical programmable interconnect circuit used to route a logic block output to a particular interconnect signal line is a pass gate multiplexer. A pass gate multiplexer includes a number of outputs that are each selectably coupled to an input through a pass gate. When a pass gate is turned on, an output is electrically coupled to the input. When the pass gate is turned off, the particular output is isolated from other outputs. By controlling the values on the gate terminals of the pass gates, circuit connections can easily be made and altered.
During operation, configuration data values stored in memory cells are used to control the operation of each programmable element. The logic blocks and interconnect routing of a programmable IC are configured by storing configuration data in configuration memory cells of each programmable element.
The versatility of reprogrammable ICs is advantageous in applications, such as aerospace, where remote reconfiguration is preferred over physical replacement. These types of applications may expose components to radiation, which can cause an error in a static random access memory (SRAM) cell. An error of this type is known as a single event upset (SEU) or soft error.
In many circuits, an SEU only has a transient effect following the particle strike and the variation will disappear in a time depending on the logic delay of the circuit. However, in circuits containing SRAM, an SEU occurring in an SRAM cell may cause the cell to change state and store an incorrect bit. When a single particle hits a memory cell, the resulting current pulse can trigger a transistor of the memory cell to pass current and invert the value stored in the memory cell. A stored high value can be inadvertently changed to a low value, and vice versa.
In a programmable IC, an SEU strike in a configuration memory cell can change the function of the programmed logic. For example, in a typical interconnect architecture of an FPGA, only one pass gate in a pass gate multiplexer is enabled at a given time. This restriction prevents shorts between signal lines. Depending on the particular memory cell that was struck, the upset may cause incorrect routing between logic blocks. In some instances, these “single event upsets” have no effect on the functionality of the chip, for example, when the static RAM cell controls a pass gate between two unused interconnect lines. In other occurrences, an SEU can change the functionality of a configured PLD such that the circuit no longer functions properly.
As operating voltages are reduced, SRAM cells used for configuration memory become more susceptible to changes in state caused by single event upsets. To reduce manufacturing costs, PLD manufacturers are aggressively reducing device sizes in programmable ICs. These smaller devices often operate at lower voltages with greater susceptibility to SEUs.
The present invention may address one or more of the above issues.